Because of the increased usage of complex digital circuits and microprocessors as signal processing circuits and for electrical isolation in multimeters and other applications, various circuits functioning cooperatively as a single system are frequently placed on different circuit boards, or are otherwise separated from one another. Such circuits, when in communication with one another, may operate in a master-slave relationship and may communicate via serial links. Where a plurality of circuit boards or circuit locations are involved, there may be a single controlling computer, or master circuit, at one location and plural slaves, or responding circuits, at other locations. In such arrangements it is necessary to determine that each of the circuits is operating properly and, if errant operation is detected due to a software or correctable hardware fault, to be able to force the slave into a known working state.
Accordingly, in the prior art it is known to include for each of the separated circuit structures, i.e., for each circuit board or each remotely located slave, as well as for the master circuit or controller, a watchdog arrangement. Typically, a watchdog circuit is present on each circuit board and monitors the operation of the specific circuit. For example, if operation of the controller is detected to stray outside predetermined limits, or boundaries, for various parameters thereof, it is necessary to reinitiate the controller. Similarly, where slave circuits are detected to be operating improperly, watchdog circuitry provided on each of the slave circuits is used to reinitiate operation.
Where the remote circuits or the slave circuits themselves include microprocessors or similar controllers, each of the "local" microprocessors (i.e., the microprocessors located on the slave circuit boards) includes a program for monitoring the various signal levels and response rates of the circuit components, both hardware and software, to determine proper operation. In the prior art, when it is determined that signal parameter values are beyond the acceptable ranges, or when it is determined that one of the circuits has become inoperative, the appropriate circuit is reinitiated by the watchdog in an attempt to regain control thereover.
However, such locally controlled reinitiation results in synchronization problems among the various slave circuits and between the master controller and the remote, reinitiated, slave circuits. The plural slave circuits must thus be resynchronized with the master controller in order to provide proper system operation, even after appropriate operation of a faulty slave circuit has been reestablished. Locally controlled reinitialization also relies on the local microprocessor being in such an operational state as to be capable of detecting and correcting the problem. This assumption, however, may not be valid, and may lead to significant operational problems.
Another prior art attempt to bring various slave circuits to operation within preset boundaries, parameters and specifications therefor attempts to overcome the synchronization problems by transmitting a break signal from the master controller to the remote slave circuit. Such a break signal typically places the transmission line in the asserted state for a time period much longer than the period for transmissions of a normal bit of information. The recited break signal is typically detected and a status bit is stored by the UART (universal asynchronous receiver/transmitter) to identify a status condition of the remote slave circuit. Reinitiation of the remote circuit occurs upon detection of the status condition of the UART by the local microprocessor of the remote circuit. Thus, the UART must generate an interrupt for the local microprocessor. However, in such an arrangement there remains a requirement for duplicating watchdog circuits and functions on each of the remote circuits, as well as the requirement for a break signal, transmitted from the remote controller as a status command, to be interpreted and translated by the local watchdog or microprocessor to a reset command in order to reinitiate proper operation of the slave circuit. Additionally, the interface between the UART and the microprocessor is required to be operational. Still more significantly, the software must be in an operational state to respond to the interrupt request from the UART. If any of these requirements is not met, the system will fail.
Similarly, if the circuitry required to decode and interpret the break signal is malfunctioning, reinitiation would similarly be impossible since the break signal could not be decoded to a reinitiation command. Moreover, for such a scheme to function properly it must be assumed that the microprocessor is in a proper communication and processing mode so that the received and decoded break signal may be properly interpreted and so that a proper interrupt sequence is initiated together with proper storage of status data.
In situations wherein the local microprocessor, whose serial communications is interrupt driven, is malfunctioning, and is unable to process interrupt vectors properly, such an arrangement would clearly fail to reinitiate operation of the slave circuit. Malfunctioning of the local microprocessor could occur due to software or hardware failure in the microprocessor or due to degraded communication between the master and slave circuits.
Moreover, in many applications microcomputers (microprocessors with on chip RAM, ROM, UARTs) . . .) are used to reduce the component count on the slaves. Typically, such microcomputers do not have full function UARTs and may not be able to receive a break signal. In this case, an even less reliable restart method is used. Thus, some type of command is transmitted over the serial link for the slave to interpret as a command to restart.
It is thus necessary to overcome the difficulties of the prior art and to provide an efficient structure for monitoring operation of a plurality of slave circuits under control of a single, remote, master. It is particularly necessary to provide simplified circuits which, through minimal interpretation of signals sent by the remote master controller, generate a very effective signal in order to reinitiate operation of malfunctioning slave circuits to predetermined states, in synchronism with the remote controller, while minimizing the complexity of the watchdog circuitry, to increase the reliability of the system.